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| ? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. 09005aef80be1fbd burst cellularram.fm - rev. d 5/19/04 en 1 ?2004 micron technology, inc. all rights reserved. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary ? burst cellularram tm mt45w4mw16bfb mt45w2mw16bfb features ? single device supports asynchronous, page, and burst operations v cc , v cc q voltages 1.70v?1.95v v cc 1.70v?2.25v v cc q (option w) 2.30v?2.70v v cc q (option v?contact factory) 2.70v?3.30v v cc q (option l?contact factory) random access time: 70ns burst mode write access continuous burst burst mode read access 4, 8, or 16 words, or continuous burst max clock rate: 104 mhz ( t clk = 9.62ns) burst initial latency: 39ns (4 clocks) @ 104 mhz t aclk: 6.5ns @ 104 mhz page mode read access sixteen-word page size interpage read access: 70ns intrapage read access: 20ns low power consumption asynchronous read < 25ma intrapage read < 15ma initial access, burst read: (39ns [4 clocks] @ 104 mhz) < 35ma continuous burst read < 15ma standby: 120a (64mb), 110a (32mb)?standard 100a (64mb), 90a (32mb)?low-power option deep power-down < 10a low-power features temperature compensated refresh (tcr) partial array refresh (par) deep power-down (dpd) mode figure 1: ball assignment 54-ball vfbga see table 1 on page 6 for ball descriptions, and figure 45 on page 52 for 54-ball mechanical drawing. part number example: mt45w2mw16bfb-706lwt options designator configuration: 4 meg x 16 mt45w 4 mx16b 2 meg x 16 mt45w 2 mx16b v cc core voltage supply: 1.80v ? mt45 w xmx16b w v cc q i/o voltage 3.0v ? mt45wxm l 16b l 1 2.5v ? mt45wxm v 16b v 1 1.8v ? mt45wxm w 16b w package 54-ball vfbga fb 54-ball vfbga?lead-free bb 1 timing 60ns access -60 1 70ns access -70 85ns access -85 options (continued) designator frequency 66 mhz 6 80 mhz 8 104 mhz 1 1 standby power standard none low-power l operating temperature range wireless (-25c to +85c) wt industrial (-40c to +85c) it 1 1. contact factory. a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 a19 a8 clk a0 a3 a5 a17 a21 a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 nc cre dq0 dq2 v cc v ss dq6 dq7 a20 nc a1 a4 a6 a7 a16 a15 a13 a10 nc
4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 2 ?2004 micron technology, inc. all rights reserved. table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 temperature compensated refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 partial array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 software access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 burst wrap (bcr[3]) default = burst no wrap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 output impedance (bcr[5]) default = outputs use full drive stre ngth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 wait configuration (bcr[8])default = wait transitions one clock before data valid/invalid . . . . . . . . . . . . 19 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 latency counter (bcr[13:11]) default = three-clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 partial array refresh (rcr[2:0]) default = fu ll array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 deep power-down (rcr[4]) default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 temperature compensated refresh (rcr[6:5]) default = +85c operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 data sheet designation: preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 3 ?2004 micron technology, inc. all rights reserved. list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2: bus operations ? asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3: bus operations ? burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 4: bus configuration register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 5: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 6: latency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 7: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 8: 64mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 9: 32mb address patterns for par (rcr[4] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11: temperature compensated refresh specifications and cond itions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12: partial array refresh specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 14: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 16: asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17: burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 19: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 20: initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 21: asynchronous read timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 22: asynchronous read timing paramete rs using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 23: asynchronous read timing parameters?page mode operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 24: burst read timing parameters?singl e access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 25: burst read timing parameters?4-wor d burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 26: burst read timing parameters?4-wor d burst with lb#/ub#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 27: burst read timing parameters?burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 28: burst read timing parameters?bcr[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 29: asynchronous write timing parameters?ce#-controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 30: asynchronous write timing parameters?lb#/ub#-controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 table 31: asynchronous write timing parameters?we#-controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 table 32: asynchronous write timing parameters using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 33: burst write timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 34: burst write timing parameters?bcr[8] = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 35: write timing parameters?b urst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 table 36: read timing parameters?burst writ e followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 37: write timing parameters?async writ e followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 38: read timing parameters?async write followed by burst re ad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 table 39: write timing parameters?async write followed by burst read?adv# low . . . . . . . . . . . . . . . . 47 table 40: read timing parameters?async write followed by burst read?adv# low . . . . . . . . . . . . . . . . . 47 table 41: burst read timing parameters?burst read follow ed by async write (we#-control) . . . . . . . . . . 48 table 42: asynchronous writ e timing parameters?burst read follow ed by async write (we#-control) . 48 table 43: burst read timing parameters?burst read follow ed by async write using adv# . . . . . . . . . . . . 49 table 44: asynchronous write timing parameters?burst read followed by async write using adv# . . . 49 table 45: write timing parameters?async write followed by async read?adv# low . . . . . . . . . . . . . . . 50 table 46: read timing parameters?async write followed by async read?adv# low . . . . . . . . . . . . . . . . 50 table 47: write timing parameters?async writ e followed by async read . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 48: read timing parameters?async write followed by async read . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 4 ?2004 micron technology, inc. all rights reserved. list of figures figure 1 ball assignment 54-ball vfbga. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 functional block diagram ? 4 meg x 16 and 2 meg x 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3 part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4 power-up initialization timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5 read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 6 write operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7 page mode read operation (adv = low). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 8 burst mode read (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 9 burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 10 wired or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 11 refresh collision during read op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 12 refresh collision during write op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 13 configuration register write in asynchronous mode fo llowed by read . . . . . . . . . . . . . . . . . . . . . . . 15 figure 14 configuration register write in synchronous mode followed by read . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 15 load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 16 read configuration regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 17 wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 18 wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 19 wait configuration during burst operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 20 latency counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 21 ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 22 output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 23 initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 24 asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 25 asynchronous read using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 26 page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 27 single-access burst read operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 28 4-word burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 29 4-word burst read operation (wit h lb#/ub#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 30 read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 31 continuous burst read with ou tput delay, bcr[8] = 0(1) for end-of-row condition . . . . . . . . . . . . . 38 figure 32 ce#-controlled asynchronous writ e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 33 lb#/ub#-controlled asynchronous write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 34 we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 35 asynchronous write using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 36 burst write operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 37 continuous burst write with output delay, bcr[8] = 0(1) for end-of-row condition . . . . . . . . . . . . 44 figure 38 burst write followed by burst read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 39 asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 40 asynchronous write foll owed by burst read?adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 41 burst read follow ed by asynchronous write (we#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 42 burst read follow ed by asynchronous write using adv#. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 43 asynchronous write fo llowed by asynchronous read?adv# low. . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 44 asynchronous write foll owed by asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 45 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 5 ?2004 micron technology, inc. all rights reserved. general description micron ? cellularram? products are high-speed, cmos dynamic random access memories developed for low-power, portable applications. the mt45w4mw16bfb is a 64mb device organized as 4 meg x 16 bits; the mt45w2mw16bfb is a 32mb device organized as 2 meg x 16 bits. these devices include an industry-standard burst mode flash inter- face that dramatically incr eases read/write bandwidth compared with other low-power sram or pseudo sram offerings. to operate seamlessly on a burst flash bus, cellular- ram products incorporate a transparent self-refresh mechanism. the hidden refresh requires no additional support from the system memory controller and has no significant impact on device read/write perfor- mance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its coun- terpart on burst mode flash devices. the refresh con- figuration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be upda ted anytime during normal operation. special attention has been focused on standby cur- rent consumption during self refresh. cellularram products include three system-accessible mechanisms used to minimize standby current. partial array refresh (par) limits refresh to only that part of the dram array that contains essential data. temperature compen- sated refresh (tcr) is used to adjust the refresh rate according to the case temperature. the refresh rate can be decreased at lower temperatures to minimize current consumption during standby. deep power- down (dpd) halts the refresh operation altogether and is used when no vital information is stored in the device. these three refresh mechanisms are accessed through the rcr. figure 2: functional block diag ram?4 meg x 16 and 2 meg x 16 note: functional block diagrams il lustrate simplified device operation. see truth table, ball descri ptions, and timing diagrams for detailed information. a[21:0] (for 64mb) a[20:0] (for 32mb) input/ output mux and buffers control logic 4,096k x 16 (2,048k x 16) dram memory array ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] address decode logic refresh configuration register (rcr) bus configuration register (bcr) 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 6 ?2004 micron technology, inc. all rights reserved. l note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchronous or page mode. wait will be asserted but should be ignored during asynchronous and page mode operations. table 1: vfbga ball descriptions vfbga assignment symbol type description a3, a4, a5, b3, b4, c3, c4, d4, h2, h3, h4, h5, g3, g4, f3, f4, e4, d3, h1, g2, h6, e3 a[21:0] input address inputs: inputs for addresses during read and write operations. addresses are internally la tched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. on the 32mb device, a21 (ball e3) is not internally connected. j2 clk input clock: synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static (high or low) during asynchronous access read and write operations and during page read access operations. j3 adv# input address valid: indicates that a valid ad dress is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# may be held low during asynchronous read and write operations. a6 cre input configuration register enable: when cre is high, write operat ions load the rcr or bcr. b5 ce# input chip enable: activate s the device when low. when ce# is high, the device is disabled and goes into standby or deep power-down mode. a2 oe# input output enable: enables the output buff ers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable: determines if a given cycle is a write cycle. if we# is low, the cycle is a write to either a configuration register or to the memory array. a1 lb# input lower byte enable. dq[7:0] b2 ub# input upper byte enable. dq[15:8] b6, c5, c6, d5, e5, f5, f6, g6, b1, c1, c2, d2, e2, f2, f1, g1 dq[15:0] input/ output data inputs/outputs. j1 wait output wait: provides data-valid feedback duri ng burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay asso ciated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. wait is hi gh-z when ce# is high. j4, j5, j6 nc ? not internally connected. d6 v cc supply device power supply: (1.70v?1.95v) powe r supply for device core operation. e1 v cc q supply i/o power supply: (1.70v?1.95v) powe r supply for inpu t/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 7 ?2004 micron technology, inc. all rights reserved. note: 1. clk may be high or low, but must be static during async read, async write, burst suspend, and dpd modes; and to achieve standby power during standby and active modes. 2. the wait polarity is configured through the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are affected. when only lb# is in select mode, dq[7:0] are affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will cons ume active power in this mode whenever addresses are changed. 5. when the device is in standby mo de, address inputs and data inputs/outp uts are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (uns witched) in order to achieve standby current. 7. dpd is maintained until rcr is reconfigured. 8. burst mode operation is initialized throug h the bus configuration register (bcr[15]). table 2: bus operations?asynchronous mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes read active x l l l h l l low-z data-out 4 write active x l l x l l l low-z data-in 4 standby standby x x h x x l x high-z high-z 5, 6 no operation idle x x l x x l x low-z x 4, 6 configuration register active xl lhlhxlow-zhigh-z dpd deep power-down x x h x x x x high-z high-z 7 table 3: bus operations?burst mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes async read active x l l l h l l low-z data-out 4 async write active x l l x l l l low-z data-in 4 standby standby x x h x x l x high-z high-z 5, 6 no operation idle x x l x x l x low-z x 4, 6 initial burst read active l l x h l l low-z data-out 4, 8 initial burst write active l l h l l x low-z data-in 4, 8 burst continue active h l x x l x low-z data-in or data-out 4, 8 burst suspend active x x l h x l x low-z high-z 4, 8 configuration register active l l h l h x low-z high-z 8 dpd deep power-down xxhxxxxhigh-zhigh-z7 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 8 ?2004 micron technology, inc. all rights reserved. part-numbering information micron cellularram devices are available in several different configurations and densities (see figure 3). figure 3: part number chart valid part number combinations after building the part number from the part num- bering chart above, please go to the micron part mark- ing decoder web site at www.micron.com/partsearch to verify that the part number is offered and valid. if the device required is not on this list, please contact the factory. device marking due to the size of the package, the micron standard part number is not printed on the top of the device. instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at www.micron.com/partsearch . to view the location of the abbreviated mark on the device, please refer to customer service note, csn-11, product mark/ label," at www.micron.com/csn . mt 45 w 4m w 16 b fb -70 6 wt es micron technology product family 45 = psram/cellularram ? memory operating core voltage w = 1.70v?1.95v address locations m = megabits operating voltage w = 1.70v?2.25v v = 2.30v?2.70v (contact factory) l = 2.70v?3.30v (contact factory) bus configuration 16 = x16 read/write operation mode b = asynchronous/page/burst package codes fb = vfbga ( 6x9g rid, 0.75mm pitch, 6.0 x 8.0 x 1.0mm) 54-ball bb = lead-free vfbga ( 6 x 9 grid, 0.75mm pitch, 6.0 x 8.0 x 1.0mm) 54-ball (contact factory) production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = -25c to +85c it = -40 to +85c (contact factory) standby power options blank = standard l = low power frequency 6=66mhz 8=80mhz 1 = 104 mhz (contact factory) access/cycle time 60 = 60ns (contact factory) 70 = 70ns 85 = 85ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 9 ?2004 micron technology, inc. all rights reserved. functional description in general, the mt45w4mw16bfb device and the mt45w2mw16bfb device ar e high-density alterna- tives to sram and pseudo sram products, popular in low-power, portable applications. the mt45w4mw16bfb device contains 67,108,864 bits organized as 4,194,304 ad dresses by 16 bits. the mt45w2mw16bfb contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits. both devices imple- ment the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asyn- chronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asynchronous read protocol. power-up initialization cellularram products incl ude an on-chip voltage sensor used to launch the power-up initialization pro- cess. initialization will configure the bcr and the rcr with their default settings (see table 4 on page 17 and table 7 on page 21). v cc and v cc q must be applied simultaneously. when they reach a stable level at or above 1.70v, the device will require 150s to complete its self-initialization process. during the initialization period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 4: power-up initialization timing bus operating modes the mt45w4mw16bfb and mt45w2mw16bfb cellularram products incorp orate a burst mode inter- face found on flash products targeting low-power, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh configuration register (rcr[7]). asynchronous mode cellularram products power up in the asynchro- nous operating mode. this mode uses the industry- standard sram control bus (ce#, oe#, we#, lb#/ ub#). read operations (figure 5) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 6) occur when ce#, we#, and lb#/ ub# are driven low. during asynchronous write operations, the oe# level is a ?don't care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub# (whichever occurs first). asynchrono us operations (page mode disabled) can either use the adv input to latch the address, or adv can be driven low during the entire read/write operation. during asynchronous operation, the clk input must be static (high or low?no transitions). wait will be driven while the device is enabled and its state should be ignored. we# low time must be limited to t cem. figure 5: read op eration (adv = low) note: adv must remain low for page mode operation . figure 6: write oper ation (adv = low) vcc vccq device initialization vcc = 1.70v device ready for normal operation t pu > 150s address valid data ce# don?t care data valid oe# we# lb#/ub# t rc = read cycle time address address valid < t cem data ce# don?t care data valid oe# we# lb#/ub# t wc = write cycle time address 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 10 ?2004 micron technology, inc. all rights reserved. page mode read operation page mode is a performance-enhancing extension to the legacy asynchronous read operation. in page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be read quickly by simply changing the low-order address. addresses a[3:0] are used to determine the members of the 16-address cellularram page. any change in addresses a[4] or higher will initiate a new t aa access time. figure 7 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. write operations do not include comparable page mode functionality. during asynchronous page mode operation, the clk input must be static (high or low?no transi- tions). ce# must be driven high upon completion of a page mode access. wait will be driven while the device is enabled and its state should be ignored. page mode is enabled by setting rcr[7] to high. write operations do not include comparable page mode functionality. adv must be driven low during all page mode read accesses. the ce# low time is limited by refresh consider- ations. ce# must not stay low longer than t cem. figure 7: page mo de read operation (adv = low) burst mode operation burst mode operations enable high-speed synchro- nous read and write operations. burst operations consist of a multi-clock sequence that must be per- formed in an ordered fashion. after ce# goes low, the address to access is latched on the next rising edge of clk that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, figure 8 on page 11) or write (we# = low, figure 9 on page 11). the size of a burst can be specified in the bcr as either fixed-length or continuous. fixed-length bursts consist of four, eight, or sixteen words. continuous bursts have the ability to start at a specified address and burst through the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is trans- ferred between the processor and cellularram device. the wait output will be asserted as soon as a burst is initiated, and will be de-asserted to indicate when data is to be transferred into (or out of ) the memory. wait will again be asserted if the burst crosses the boundary between 128-word rows. once the cellular- ram device has restored the previous row's data and accessed the next row, wait will be de-asserted and the burst can continue (see figure 31 on page 38). the processor can access other devices without incurring the timing penalty of the initial latency for a new burst by suspending burst mode. bursts are sus- pended by stopping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to dis- able the cellularram outp uts; otherwise, oe# can remain low. note that the wait output will continue to be active, and as a resu lt no other devices should directly share the wait connection to the controller. to continue the burst sequence, oe# is taken low, then clk is restarted after valid data is available on the bus. the ce# low time is limited by refresh consider- ations. ce# must not stay low longer than t cem unless row boundaries are crossed at least every t cem. if a burst suspension will cause ce# to remain low for longer than t cem, ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle. data ce# don?t care oe# we# lb#/ub# address add[0] add[1] add[2] add[3] d[1] d[2] d[3] t aa t apa < t cem t apa t apa d[0] 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 11 ?2004 micron technology, inc. all rights reserved. figure 8: burst mode read (4-word burst) 1 note: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. figure 9: burst mode write (4-word burst) 1 note: 1. non-default bcr settings: latency code two (three cl ocks); wait active low; wait asserted during delay. a[21:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# latency code 2 (3 clocks) clk undefined don?t care read burst identified (we# = high) address valid a[21:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# address valid latency code 2 (3 clocks) clk don?t care write burst identified (we# = low) 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 12 ?2004 micron technology, inc. all rights reserved. mixed-mode operation the device can support a combination of synchro- nous read and asynchronous write operations when the bcr is configured for synchronous opera- tion. the asynchronous write operation requires that the clock (clk) remain static (high or low) during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# must return high when transitioning between mixed-mode operations. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operat ion facilitates a seamless interface to legacy burst mode flash memory control- lers. see figure 39 on page 46 for the ?asynchronous write followed by burst read? timing diagram. wait operation the wait output on a cellularram device is typi- cally connected to a shared, system-level wait signal (see figure 10 below). the shared wait signal is used by the processor to coordinate transactions with mul- tiple memories on the synchronous bus. figure 10: wired or wait configuration once a read or write operation has been initi- ated, wait goes active to indicate that the cellular- ram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to the memory controller when data will be accepted into the cellu- larram device. when wait transitions to an inactive state, the data burst will progress on successive clock edges. ce# must remain asserted during wait cycles (wait asserted and wait configuration bcr[8] = 1). bringing ce# high during wait cycles may cause data corruption. (note that for bcr[8] = 0, the actual wait cycles end one cycle after wait de-asserts, and for row boundary crossings, start one cycle after the wait signal asserts.) the wait output also performs an arbitration role when a read or write operation is launched while an on-chip refresh is in progress. if a collision occurs, the wait pin is asserted for additional clock cycles until the refresh has completed (see figures 11 and 12 on page 13). when the refresh operation has com- pleted, the read or write operation will continue normally. wait is also asserted when a continuous read or write burst crosses a row boundary. the wait asser- tion allows time for the new row to be accessed, and permits any pending refresh operations to be per- formed. lb#/ub# operation the lb# enable and ub# enable signals support byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dqs. the dqs associated with a disabled byte are put into a high-z state during a read operat ion. during write opera- tions, any disabled bytes will not be transferred to the ram array and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (high) during an operation, the device will disable the data bus from receiving or transmitting data. although the device will seem to be deselected, it remains in an active mode as long as ce# remains low. cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 13 ?2004 micron technology, inc. all rights reserved. figure 11: refresh collision during read operation 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. figure 12: refresh collis ion during write operation 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. a[21:0] adv# ce# oe# we# wait dq[15:0] clk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d[2] d[1] d[3] valid address additional wait states inserted to allow refresh completion. lb#/ub# undefined don?t care d[0] high-z a[21:0] adv# ce# oe# we# wait dq[15:0] clk d[1] d[0] d[3] d[2] valid address additional wait states inserted to allow refresh completion. lb#/ub# don?t care v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol high-z 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 14 ?2004 micron technology, inc. all rights reserved. low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write operation, or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. temperature compensated refresh temperature compensated refresh (tcr) is used to adjust the refresh rate depending on the device operat- ing temperature. dram technology requires increas- ingly frequent refresh operations to maintain data integrity as temperatures increase. more frequent refresh is required due to increased leakage of the dram capacitive storage elements as temperatures rise. a decreased refresh rate at lower temperatures will facilitate a savings in standby current. tcr allows for adequate refresh at four different temperature thresholds (+15c, +45c, +70c, and +85c). the setting selected must be for a temperature higher than the case temp erature of the cellularram device. for example, if the case temperature is +50c, the system can minimize self refresh current consump- tion by selecting the +70 c setting. the +15c and +45c settings would result in inadequate refreshing and cause data corruption. partial array refresh partial array refresh (par) restricts refresh operation to a portion of the total memory array. this feature enables the device to reduce standby current by refreshing only that part of the memory array required by the host system. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 8 and 9 on page 22). read and write operations to address ranges receiving refresh will not be affected. data stored in addresses not receiving refresh will become corrupted. when re-enabling additional portions of the array, the new portions are available immediately upon writing to the rcr. deep power-do wn operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled by rewriting the rcr, the cellularram device will require 150s to perform an initialization procedure before normal operations can resume. dur- ing this 150s period, the current consumption will be higher than the specified standby levels, but consider- ably lower than the active current specification. dpd cannot be enabled or disabled by writing to the rcr using the software access sequence; the rcr should be accessed using cre instead. configuratio n registers two user-accessible configuration registers define the device operation. the bus configuration register (bcr) defines how the cellularram interacts with the system memory bus and is ne arly identical to its coun- terpart on burst mode flash devices. the refresh config- uration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up, and can be updated any time the devices are operating in a standby state. access using cre the configuration registers are loaded using either a synchronous or an asynchronous write operation when the configuration register enable (cre) input is high (see figures 13 and 14 on page 15). when cre is low, a read or write operation will access the memory array. the register values are placed on address pins a[21:0]. in an asynchronous write, the values are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? access using cre is write only. the bcr is accessed when a[19] is high; the rcr is accessed when a[19] is low. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 15 ?2004 micron technology, inc. all rights reserved. figure 13: configuration regist er write in asynchronous mode followed by read array operation note: 1. a[19] = low to load rcr; a[19] = high to load bcr. figure 14: configuration regist er write in synchronous mode followed by read array operation 1 note: 1. non-default bcr settings: latency code two (three clocks); wait active low; wait asserted during delay. 2. a[19] = low to load rcr; a[19] = high to load bcr. 3. ce# must remain low to complete a bu rst-of-one write. wait must be monitored? additional wait cycles caused by refresh collisions require a corresponding number of additional ce# low cycles. a[21:0] (except a19) clk opcode address address data valid a19 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate control register access write address bus value to control register cre t avs t avh t avh t avs t vp t vph t cbph t wp t cw don?t care select control register clk a[21:0] (except a19) a19 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t csp t sp t hd high-z don?t care opcode address high-z t cw latch control register value latch control register address t cbph 3 data valid address 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 16 ?2004 micron technology, inc. all rights reserved. software access software access of the configuration registers uses a sequence of asynchronous read and asynchronous write operations. the contents of the configuration registers can be read or modified using the software sequence. the configuration registers are loaded using a four- step sequence consisting of two asynchronous read operations followed by two asynchronous write operations (see figure 15). the read sequence is virtu- ally identical except that an asynchronous read is performed during the fourth operation (see figure 16). the address used during all read and write opera- tions is the highest address of the cellularram device being accessed (3fffffh for 64mb, and 1fffffh for 32mb); the contents of this address are not changed by using this sequence. the data value presented during the third operation (write) in the sequence defines whether the bcr or the rcr is to be accessed. if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the sequence will access the bcr. during the fourth oper- ation, the data bus is used to transfer data in to or out of the configuration registers. the use of the software sequence does not affect the ability to perform the standard (cre-controlled) method of loading the configuration registers. how- ever, the software nature of this access mechanism eliminates the need for the control register enable (cre) pin. if the software mechanism is used, the cre pin can simply be tied to v ss . the port line often used for cre control purposes is no longer required. software access of the rcr should not be used to enter or exit dpd. figure 15: load configuration register figure 16: read co nfiguration register note: ce# must be high fo r 150ns before performing the cycle that reads a configuration register. address (max) address (max) address (max) address (max) xxxxh xxxxh rcr: 0000h bcr: 0001h cr value in a ddress ce# oe# we# lb#/ub# data don't care read read write write address (max) address (max) address (max) address (max) xxxxh xxxxh cr value out address ce# oe# we# lb#/ub# data don't care read read write read rcr: 0000h bcr: 0001h note 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 17 ?2004 micron technology, inc. all rights reserved. bus configuration register the bcr defines how the cellularram device inter- acts with the system memory bus. page mode opera- tion is enabled by a bit contained in the rcr. table 4 on page 17 describes the control bits in the bcr. at power-up, the bcr is set to 9d4fh. the bcr is accessed using cre and a[19] high, or through the configuration register software sequence with dq = 0001h on the third cycle. table 4: bus configuratio n register definition note: 1. all burst writes are continuous. a13 13 12 11 0 latency counter 3 21 wait polarity 4 5 wait configuration (wc) clock configuration (cc) 6 7 8 output impedance burst wrap (bw)* 14 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 operation mode synchronous burst access mode asynchronous access mode (default) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4?reserved code 5?reserved code 6?reserved code 7?reserved 0 1 wait polarity active low active high (default) bcr[10] 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) 0 1 output impedance full drive (default) 1/4 drive bcr[5] burst wrap (note 1) burst wraps within the burst length burst no wrap (default) bcr[3] bcr[1] bcr[0] burst length (note 1) bcr[2] 15 burst length (bl)* reserved reserved 9 10 reserved operating mode reserved 21?20 a14 a15 a[18:16] 0 1 register select select rcr select bcr must be set to "0" 19 18?16 register select reserved a19 a[21:20] reserved must be set to "0" must be set to "0" must be set to "0" must be set to "0" all must be set to "0" bcr[8] 0 1 clock configuration not supported rising edge (default) bcr[6] bcr[15] bcr[19] 0 1 0 0 0 1 0 1 1 1 1 0 1 1 4 words 8 words 16 words continuous burst (default) 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 18 ?2004 micron technology, inc. all rights reserved. burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words the device outputs during a burst read operation. the device sup- ports a burst length of 4, 8, or 16 words. the device can also be set in continuous bu rst mode where data is out- put sequentially without regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address. write bursts are always per- formed using continuous burst mode. burst wrap (bcr[3]) default = burst no wrap the burst wrap option determines if a 4-, 8-, or 16- word burst read wraps within the burst length, or steps through sequential addresses. if the wrap option is not enabled, the device outputs data from sequential addresses without regard to burst boundaries; the internal address wraps to 000000h if the device is read past the last address. output impedance (bcr[5]) default = outputs use full drive strength the output driver strength can be altered to adjust for different data bus loading scenarios. the reduced- strength option will be more than adequate in stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced-drive-strength option is included to minimize noise generated on the data bus during read operations. normal output impedance should be selected when using a discrete cellularram device in a more heavily loaded data bus environment. partial drive is approximately one-quar- ter full drive strength. outputs are configured at full drive strength during testing. table 5: sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-word burst length continuous burst bcr[3] wrap (decimal) linear linear linear linear 0yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 -8-9-10-11-12-13-14- 15 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7 -8-9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8 -9-10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9 -10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11- 12-13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12- 13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13- 14-15-0-1-2-3-4-5 6-7-8-9-10-11-12- 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15 -0-1-2-3-4-5-6 7-8-9-10-11-12-13-? ... ... ... 14 14-15-0-1-2-3-4-5- 6-7-8-9-10-11-12-13 14- 15-16-17-18-19-20-.. 15 15-0-1-2-3-4-5-6-7-8-9-10- 11-12-13-14 15-16-17- 18-19-20-21.. 1no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 -8-9-10-11-12-13-14- 15 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8 -9-10-11-12-13-14-15- 16 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5-6-7-8-9 -10-11-12-13-14-15-16- 17 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3- 4-5-6-7-8-9-10-11-12-13-14- 15-16-17-18 3-4- 5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8-9-10-11- 12-13-14-15-16-17-18-19 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9-10-11- 12-13-...-15-16-17-18-19-20 5-6-7-8-9-10-11? 6 6-7-8-9-10-11-12-13 6-7-8-9-10-11-12- 13-14-...-16-17-18-19-20-21 6-7-8-9-10-11-12? 7 7-8-9-10-11-12-13-14 7-8-9-10-11-12-13- 14-...-17-18-19-20-21-22 7-8-9-10-11-12-13? ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26- 27-28-29 14-15-16-17-18-19-20-? 15 15-16-17-18-19-20-...-24-25-26-27- 28-29-30 15-16-17-18-19-20-21-? 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 19 ?2004 micron technology, inc. all rights reserved. wait configuration (bcr[8]) default = wait transitions one clock before data valid/invalid the wait configuration bit is used to determine when wait transitions between the asserted and the de-asserted state with respect to valid data presented on the data bus. the memory controller will use the wait signal to coordinate data transfer during synchronous read and write operations. when bcr[8] = 0, data will be valid or invalid on the clock edge immediately after wait transitions to the de-asserted or asserted state, respectively (figures 17 and 19). when a8 = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid (figures 18 and 16). wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the de-asserted state. figure 17: wait configuration (bcr[8] = 0) note: 1. note: data valid/invalid immediately after wait transitions (bcr[8] = 0). see figure 19. figure 18: wait configuration (bcr[8] = 1) note: 1. note: valid/invalid data delayed for one clock after wait transitions (bcr[8] = 1). see figure 19. figure 19: wait configur ation during burst operation 1 note: 1. non-default bcr setti ng: wait active low. wait dq[15:0] clk data[0] data[1] data immediately valid (or invalid) high-z wait d[15:0] clk data[0] data valid (or invalid) after one clock delay high-z wait wait dq[15:0] clk d[0] d[1] bcr[8] = 0 data valid in current cycle bcr[8] = 1 data valid in next cycle don?t care d[2] d[3] d[4] 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 20 ?2004 micron technology, inc. all rights reserved. latency counter (bcr[13:11]) default = three-clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. only latency code two (thr ee clocks) or latency code three (four clocks) is allowed (see table 6 and figure 20 below). operating mode (bcr[15]) default = asynchronous operation the operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation. note: 1. clock rates below 50 mhz are allowed as long as t csp specifications are met. figure 20: latency counter table 6: latency configuration latency configuration code max input clk frequency (mhz) -701 -708 -706, -856 2 (3 clocks) 66 (15.2ns) 53 (18.75ns) 44 1 (22.7ns) 3 (4 clocks) ? default 104 (9.62ns) 80 (12.5ns) 66 (15.2ns) a[21:0] adv# dq[15:0] clk code 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output code 3 (default) dq[15:0] don?t care undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid address 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 21 ?2004 micron technology, inc. all rights reserved. refresh configuration register the refresh configuration register (rcr) defines how the cellularram device performs its transparent self refresh. altering the refresh parameters can dra- matically reduce current consumption during standby mode. page mode control is also embedded into the rcr. table 7 below describes the control bits used in the rcr. at power-up, the rcr is set to 0070h. the rcr is accessed using cre and a[19] low; or through the configuration register software access sequence with dq = 0000h on the third cycle (see con- figuration registers on page 14.) partial array refresh (rcr[2:0]) default = full array refresh the par bits restrict refresh operation to a portion of the total memory array. this feature allows the device to reduce standby current by refreshing only that part of the memory array required by the host sys- tem. the refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. the mapping of these partitions can start at either the beginning or the end of the address map (see tables 8 and 9 on page 22). table 7: refresh configuration register mapping par a4 a3 a2 a1 a0 read configuration register address bus 4 5 1 2 3 0 reserved reserved 6 a5 0 1 deep power-down dpd enable dpd disable (default) rcr[4] tcr rcr[6] rcr[5] 1 1 1 1 0 0 0 0 maximum case temp. +85?c (default) +70?c +45?c +15?c a6 all must be set to "0" a[18:8] 18?8 19 21?20 register select reserved a[21:20] a19 0 1 register select select rcr select bcr rcr[19] all must be set to "0" rcr[1] 0 0 1 1 rcr[0] 0 1 0 1 refresh coverage full array (default) bottom 1/2 array bottom 1/4 array bottom 1/8 array rcr[2] 0 0 0 0 00 1 0 1 1 1 0 1 11 1 none of array top 1/2 array top 1/4 array top 1/8 array dpd must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 22 ?2004 micron technology, inc. all rights reserved. deep power-down (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellular- ram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been re-enabled, the cellularram device will require 150s to perform an initializati on procedure before normal operations can resume. deep power-down is enabled when rcr[4] = 0, and remains enabled until rcr[4] is set to ?1.? dpd should not be enabled or disabled with the software access sequence; instead, use cre to access the rcr. temperature compensated refresh (rcr[6:5]) default = +85c operation the tcr bits allow for adeq uate refresh at four dif- ferent temperature thresholds (+15c, +45c, +70c, and +85c). the setting sel ected must be for a tem- perature higher than the case temperature of the cellularram device. if the case temperature is +50c, the system can mini mize self refresh current consumption by selecting the +70c setting. the +15c and +45c settings wo uld result in inadequate refreshing and cause data corruption. page mode operation (rcr[7]) default = disabled the page mode operation bit determines whether page mode is enabled for asynchronous read opera- tions. in the power-up default state, page mode is dis- abled. table 8: 64mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?3fffffh 4 meg x 16 64mb 0 0 1 one-half of die 000000h?1fffffh 2 meg x 16 32mb 0 1 0 one-quarter of die 000000h?0fffffh 1 meg x 16 16mb 0 1 1 one-eighth of die 000000h?07ffffh 512k x 16 8mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 200000h?3fffffh 2 meg x 16 32mb 1 1 0 one-quarter of die 300000h?3fffffh 1 meg x 16 16mb 1 1 1 one-eighth of die 380000h?3fffffh 521k x 16 8mb table 9: 32mb address patterns for par (rcr[4] = 1) rcr[2] rcr[1] rcr[0] active section address space size density 0 0 0 full die 000000h?1fffffh 2 meg x 16 32mb 0 0 1 one-half of die 000000h?0fffffh 1 meg x 16 16mb 0 1 0 one-quarter of die 000000h?07ffffh 512k x 16 8mb 0 1 1 one-eighth of die 000000h?03ffffh 256k x 16 4mb 1 0 0 none of die 0 0 meg x 16 0mb 1 0 1 one-half of die 100000h?1fffffh 1 meg x 16 16mb 1 1 0 one-quarter of die 180000h?1fffffh 512k x 16 8mb 1 1 1 one-eighth of die 1c0 000h?1fffffh 256k x 16 4mb 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 23 ?2004 micron technology, inc. all rights reserved. absolute maximum ratings* voltage to any ball except v cc , v cc q relative to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.50v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss . . -0.2v to +2.45v voltage on v cc q supply relative to v ss . -0.2v to +4.0v storage temperature (plastic). . . . . . . . -55oc to +150oc operating temperature (case) wireless. . . . . . . . . . . . . . . . . . . . . . . . . . -25oc to +85oc industrial . . . . . . . . . . . . . . . . . . . . . . . . -40oc to +85oc soldering temperature and time 10s (lead only) . . . . . . . . . . . . . . . . . . . . . . . . . . . +260oc *stresses greater than those listed may cause per- manent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect reliability. note: 1. input signals may overshoot to vccq + 1.0v for periods less than 2ns during transitions. 2. input signals may undershoot to vss - 1.0v for periods less than 2ns during transitions 3. bcr[5:4] = 00b. 4. this parameter is specified with the out puts disabled to avoid external loading effects. the user must add the current requir ed to drive output capacitance expected in the actual system. 5. i sb (max) values measured with par set to full array and tcr set to +85c. in order to achieve low standby current, all inputs must be driven to either v cc q or v ss . i sb might be slightly higher for up to 500ms after power-up, or after changes to the par array partition. table 10: electrical characte ristics and operating conditions wireless temperature (-25oc < t c < +85oc); industrial temperature (-40oc < t c < +85oc) description conditions symbol min max units notes supply voltage v cc 1.70 1.95 v i/o supply voltage v cc q w: 1.8v 1.70 2.25 v v: 2.5v 2.30 2.70 v l: 3.0v 2.70 3.30 v input high voltage v ih 1.40 v cc q + 0.2 v 1 input low voltage v il -0.20 0.4 v 2 output high voltage i oh = -0.2ma v oh 0.80 v cc qv3 output low voltage i ol = +0.2ma v ol 0.20 v cc qv 3 input leakage current v in = 0 to v cc qi li 1a output leakage current oe# = v ih or chip disabled i lo 1a operating current asynchronous random read/write v in = v cc q or 0v chip enabled, i out = 0 i cc 1 -70 25 ma 4 -85 20 asynchronous page read i cc 1p -70 15 ma 4 -85 12 initial access, burst read/write i cc 2 104 mhz 35 ma 4 80 mhz 35 66 mhz 30 continuous burst read/write i cc 3 104 mhz 20 ma 4 80 mhz 18 66 mhz 15 standby current v in = v cc q or 0v ce# = v cc q i sb 64mb?std 120 a 5 64mb?opt. l 100 32mb?std 110 32mb?opt. l 90 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 24 ?2004 micron technology, inc. all rights reserved. note: i tcr (max) values measured wi th par set to full array. note: i par (max) values measured with tcr set to 85c. i par might be slightly higher for up to 500ms after changes to the par array partition. table 11: temperature compensated re fresh specifications and conditions description conditions symbol density max case temperatures standard power (no desig.) low-power option (l) units temperature compensated refresh standby current v in = v cc q or 0v ce# = v cc q i tcr 64mb +85c 120 100 a +70c 105 85 a +45c 85 65 a +15c 70 50 a 32mb +85c 110 90 a +70c 95 75 a +45c 80 60 a +15c 70 50 a table 12: partial array refresh specifications and conditions description conditions symbol density array partition standard power (no desig.) low-power option (l) units partial array refresh standby current v in = v cc q or 0v, ce# = v cc q i par 64mb full 120 100 a 1/2 115 95 a 1/4 110 90 a 1/8 105 85 a 07050a 32mb full 110 90 a 1/2 105 85 a 1/4 100 80 a 1/8 95 75 a 07050a table 13: deep power-down specifications description conditions symbol typ units deep power-down v in = v cc q or 0v; +25c i zz 10 a 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 25 ?2004 micron technology, inc. all rights reserved. note: 1. these parameters are verified in device characterization and are not 100% tested. figure 21: ac input/outp ut reference waveform note: 1. ac test inputs are driven at v cc q for a logic 1 and v ss for a logic 0. input rise and fall times (10% to 90%) < 1.6ns. 2. input timing begins at v cc /2. due to the possibility of a difference between v cc and v cc q, the input test point may not be shown to scale. 3. output timing ends at v cc q/2. figure 22: output load circuit note: all tests are performed with the outputs configured for full drive strength (bcr[5] = 0). table 14: capacitance description conditions symbol min max units notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6 pf 1 input/output capacitance (dq) c io 3.5 6 pf 1 output test points input 1 v cc q v ss v cc q/2 3 v cc /2 2 dut vccq r1 r2 30pf test point table 15: output load circuit v cc q r1/r2 1.8v 2.7k ? 2.5v 3.7k ? 3.0v 4.5k ? 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 26 ?2004 micron technology, inc. all rights reserved. note: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. page-mode en abled only. 3. high-z to low-z timings are tested wi th the circuit shown in figure 22 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 4. low-z to high-z timings are tested wi th the circuit shown in figure 22 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. table 16: asynchronous read cycle timing requirements 1 parameter symbol -70x -856 units notes min max min max address access time t aa 70 85 ns adv# access time t aadv 70 85 ns page access time t apa 20 25 ns address hold from adv# high t avh 55ns address setup to adv# high t avs 10 10 ns lb#/ub# access time t ba 70 85 ns lb#/ub# disable to dq high-z output t bhz 88ns4 lb#/ub# enable to low-z output t blz 10 10 ns 3 maximum ce# pulse width t cem 88s2 ce# low to wait valid t cew 17.517.5ns chip select access time t co 70 85 ns ce# high between subsequent asynchronous operations t cph 55ns ce# low to adv# high t cvs 10 10 ns chip disable to dq and wait high-z output t hz 88ns4 chip enable to low-z output t lz 10 10 ns 3 output enable to valid output t oe 20 20 ns output hold from address change t oh 55ns output disable to dq high-z output t ohz 88ns4 output enable to low-z output t olz 55ns3 page cycle time t pc 20 25 ns read cycle time t rc 70 85 ns adv# pulse width low t vp 10 10 ns adv# pulse width high t vph 10 10 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 27 ?2004 micron technology, inc. all rights reserved. note: 1. all tests are performed with the outputs conf igured for full drive strength (bcr[5] = 0). 2. when configured for synchronous mode (bcr[15] = 0), a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by ei ther of the following two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. 4. low-z to high-z timings are tested wi th the circuit shown in figure 22 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 5. high-z to low-z timings are tested wi th the circuit shown in figure 22 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . table 17: burst read cy cle timing requirements 1 parameter symbol -701 -708 -706, -856 units notes min max min max min max burst to read access time t aba 35 46.5 56 ns clk to output delay t aclk 7911ns burst oe# low to output delay t boe 20 20 20 ns ce# high between subsequent mixed-mode operations t cbph 555ns 2 maximum ce# pulse width t cem 888s2 ce# low to wait valid t cew 17.517.517.5ns clk period t clk 9.62 20 12.5 20 15 20 ns 3 ce# setup time to active clk edge t csp 4 20 4.5 20 5 20 ns hold time from active clk edge t hd 222ns chip disable to dq and wait high-z output t hz 8 8 8 ns 4 clk rise or fall time t khkl 1.6 1.6 1.6 ns clk to wait valid t khtl 7911ns clk to dq high-z output t khz 383838ns4 clk to low-z output t klz 252525ns5 output hold from clk t koh 2 2 2 ns clk high or low time t kp 3 4 5 ns output disable to dq high-z output t ohz 8 8 8 ns 4 output enable to low-z output t olz 5 5 5 ns 5 setup time to active clk edge t sp 3 3 3 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 28 ?2004 micron technology, inc. all rights reserved. note: 1. high-z to low-z timings are tested wi th the circuit shown in figure 22 on page 25. the low-z timings measure a 100mv transition away from the high-z (v cc q/2) level toward either v oh or v ol . 2. low-z to high-z timings are tested wi th the circuit shown in figure 22 on page 25. the high-z timings measure a 100mv transition from either v oh or v ol toward v cc q/2. 3. we# low time must be limited to t cem (8s). table 18: asynchronous write cycle timing requirements parameter symbol -70x -856 units notes min max min max address and adv# low setup time t as 00ns address hold from adv# going high t avh 55ns address setup to adv# going high t avs 10 10 ns address valid to end of write t aw 70 85 ns lb#/ub# select to end of write t bw 70 85 ns ce# low to wait valid t cew 1 7.5 1 7.5 ns async address-to-bur st transition time t cka 70 85 ns ce# low to adv# high t cvs 10 10 ns chip enable to end of write t cw 70 85 ns data hold from write time t dh 00ns data write setup time t dw 23 23 ns chip disable to wait high-z output t hz 88ns chip enable to low-z output t lz 10 10 ns 1 end write to low-z output t ow 55ns 1 adv# pulse width t vp 10 10 ns adv# pulse width high t vph 10 10 ns adv# setup to end of write t vs 70 85 ns write cycle time t wc 70 85 ns write to dq high-z output t whz 88ns 2 write pulse width t wp 46 55 ns 3 write pulse width high t wph 10 10 ns write recovery time t wr 00ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 29 ?2004 micron technology, inc. all rights reserved. note: 1. when configured for synchronous mode (bcr[15] = 0), a refresh opportunity must be provided every t cem. a refresh opportunity is satisfied by ei ther of the following two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. table 19: burst write cycle timing requirements parameter symbol -701 -708 -706, -856 units notes min max min max min max ce# high between subsequent mixed-mode operations t cbph 555ns 1 minimum ce# pulse width t cem 888s1 ce# low to wait valid t cew 17.517.517.5ns clock period t clk 9.62 20 12.5 20 15 20 ns 2 ce# setup to clk active edge t csp 4 20 4.5 20 5 20 ns hold time from active clk edge t hd 222ns chip disable to wait high-z output t hz 888ns clk rise or fall time t khkl 1.6 1.6 1.6 ns clock to wait valid t khtl 7911ns clk high or low time t kp 345ns setup time to activate clk edge t sp 3 3 3 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 30 ?2004 micron technology, inc. all rights reserved. timing diagrams figure 23: initialization period t pu vcc, vccq = 1.70v vcc (min) device ready for normal operation table 20: initializatio n timing parameters parameter symbol -70x -856 units note min max min max initialization period (require d before normal operations) t pu 150 150 s 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 31 ?2004 micron technology, inc. all rights reserved. figure 24: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t cbph t aa t hz t ba high-z high-z t rc t co t bhz t ohz t hz t oe t cew valid output high-z undefined don?t care t blz t lz t olz table 21: asynchronous re ad timing parameters symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aa 70 85 ns t hz 88ns t ba 70 85 ns t lz 10 10 ns t bhz 8 8 ns t oe 20 20 ns t blz 10 10 ns t ohz 8 8 ns t cbph 5 5 ns t olz 5 5 ns t cew 1 7.5 1 7.5 ns t rc 70 85 ns t co 70 85 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 32 ?2004 micron technology, inc. all rights reserved. figure 25: asynchronous read using adv# a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t vph t cbph t aadv t aa t vp t hz t ba high-z high-z t cvs t co t blz t bhz t ohz t hz t lz t oe t olz valid output t avh t avs high-z undefined don?t care t cew v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il table 22: asynchronous read timing parameters using adv# symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aa 70 85 ns t co 70 85 ns t aadv 70 85 ns t cvs 10 10 ns t avh 5 5 ns t hz 88ns t avs 10 10 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 8 8 ns t ohz 8 8 ns t blz 10 10 ns t olz 5 5 ns t cbph 5 5 ns t vp 10 10 ns t cew 1 7.5 1 7.5 ns t vph 10 10 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 33 ?2004 micron technology, inc. all rights reserved. figure 26: page mode read a[3:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t cbph t aa t hz t ba high-z high-z t co t cem t blz t bhz t ohz t hz t lz t oe t olz t cew high-z undefined don?t care a[21:4] valid address valid address valid address valid address t rc valid output t apa t cbph t pc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t oh valid output valid output valid output table 23: asynchronous read timing parameters?page mode operation symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aa 70 85 ns t hz 8 8 ns t apa 20 25 ns t lz 10 10 ns t ba 70 85 ns t oe 20 20 ns t bhz 8 8 ns t oh 5 5 ns t blz 10 10 ns t ohz 8 8 ns t cbph 5 5 ns t olz 5 5 ns t cem 88s t pc 20 25 ns t cew 1 7.5 1 7.5 ns t rc 70 85 ns t co 70 85 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 34 ?2004 micron technology, inc. all rights reserved. figure 27: single-access burst read operation 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba t cem valid output valid address high-z t koh t ohz t sp t hd lb#/ub# v ih v il t csp high-z t olz high-z t hd t hd t sp t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe table 24: burst read timing parameters?single access symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hz 8 8 8 ns t aclk 7 9 11ns t khkl 1.6 1.6 1.6 ns t boe 20 20 20 ns t khtl 7 911ns t cem 888s t koh 2 2 2 ns t cew 17.517.517.5ns t kp 345ns t clk 9.62 20 12.5 20 15 20 ns t ohz 8 8 8 ns t csp 4204.520520ns t olz 5 5 5 ns t hd 2 2 2 ns t sp 3 3 3 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 35 ?2004 micron technology, inc. all rights reserved. figure 28: 4-word burst read operation 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t khkl t hd t aba high-z t koh t hz t hd t sp t hd lb#/ub# v ih v il high-z t olz t cbph t csp t cem t sp t hd t sp t hd t ohz t kp t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe valid address high-z table 25: burst read timing parameters?4-word burst symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hz 8 8 8 ns t aclk 7911ns t khkl 1.6 1.6 1.6 ns t boe 20 20 20 ns t khtl 7911ns t cbph 555ns t koh 2 2 2 ns t cem 888s t kp 345 ns t cew 17.517.517.5ns t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t olz 5 5 5 ns t csp 4204.520520ns t sp 3 3 3 ns t hd 2 2 2 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 36 ?2004 micron technology, inc. all rights reserved. figure 29: 4-word burst re ad operation (with lb#/ub#) 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. bcr configured with a burst length of four. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t hd t aba high-z t koh t khz t khz t klz t hz t hd t sp t hd lb#/ub# v ih v il high-z t olz high-z t cbph t csp t cem t sp t hd t sp t hd t ohz undefined don?t care read burst identified (we# = high) t cew high-z t aclk t khtl valid output valid output valid output t boe valid address table 26: burst read timing para meters?4-word burst with lb#/ub# symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hz 8 8 8 ns t aclk 7911ns t khtl 7911ns t boe 20 20 20 ns t khz 383838ns t cbph 555ns t klz 252525ns t cem 888s t koh 2 2 2 ns t cew 17.517.517.5ns t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t olz 5 5 5 ns t csp 4204.520520ns t sp 3 3 3 ns t hd 2 2 2 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 37 ?2004 micron technology, inc. all rights reserved. figure 30: read burst suspend 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t hd high-z t olz t aclk lb#/ub# v ih v il t clk t sp t hd t csp t sp t hd t sp t hd t koh valid output valid output undefined don?t care valid address high-z t cbph t cem t hz t ohz valid output valid output valid output valid output t boe t ohz t boe t olz valid address high-z table 27: burst read timing parameters?burst suspend symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aclk 7911ns t hd 222ns t boe 20 20 20 ns t hz 8 8 8 ns t cbph 555ns t koh 222ns t cem 888s t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t olz 5 5 5 ns t csp 4204.520520ns t sp 3 3 3 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 38 ?2004 micron technology, inc. all rights reserved. figure 31: continuous burst read showing an output delay with bcr[8] = 0 for end-of-row condition 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. 3. wait will be asserted (2 x lc) cycles (bcr[8] = 0; wa it asserted during delay). lc = latency code (bcr[13:11]). 4. ce# must not remain low longer than t cem. t aclk t koh a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t khtl t khtl t clk lb#/ub# v ih v il valid output valid output valid output don?t care valid output note 3 note 4 table 28: burst read timi ng parameters?bcr[8] = 0 symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aclk 7911ns t khtl 7911ns t clk 9.62 20 12.5 20 15 20 ns t koh 2 2 2 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 39 ?2004 micron technology, inc. all rights reserved. figure 32: ce#-controll ed asynchronous write a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in valid address high-z high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out t whz t bw t lz t dh t as t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il high-z table 29: asynchronous write ti ming parameters?ce#-controlled symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 88ns t cw 70 85 ns t wp 46 55 ns t dh 00ns t wph 10 10 ns t dw 23 23 ns t wr 00ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 40 ?2004 micron technology, inc. all rights reserved. figure 33: lb#/ ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t dh t as t wp t wph high-z high-z table 30: asynchronous write ti ming parameters?lb#/ub#-controlled symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t lz 10 10 ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 8 8 ns t cw 70 85 ns t wp 46 55 ns t dh 0 0 ns t wph 10 10 ns t dw 23 23 ns t wr 0 0 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 41 ?2004 micron technology, inc. all rights reserved. figure 34: we#-controlle d asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address t wc t cew t hz valid input t aw don?t care t wr t dw dq[15:0] out v oh v ol t whz t bw t cw t lz t wp t dh t ow t as t wph high-z high-z high-z table 31: asynchronous write timing parameters?we#-controlled symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t lz 10 10 ns t aw 70 85 ns t ow 55ns t bw 70 85 ns t wc 70 85 ns t cew 1 7.5 1 7.5 ns t whz 8 8 ns t cw 70 85 ns t wp 46 55 ns t dh 0 0 ns t wph 10 10 ns t dw 23 23 ns t wr 0 0 ns t hz 88ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 42 ?2004 micron technology, inc. all rights reserved. figure 35: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il a[21:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z high-z t cew t hz valid input t vs don?t care t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t as t wph t as t vph t avh t avs t vp t aw high-z table 32: asynchronous write timing parameters using adv# symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t hz 88ns t avh 5 5 ns t lz 10 10 ns t avs 10 10 ns t ow 55ns t aw 70 85 ns t vp 10 10 ns t bw 70 85 ns t vph 10 10 ns t cew 1 7.5 1 7.5 ns t vs 70 85 ns t cw 70 85 ns t whz 8 8 ns t dh 0 0 ns t wp 46 55 ns t dw 23 23 ns t wph 10 10 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 43 ?2004 micron technology, inc. all rights reserved. figure 36: burst write operation 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t hd t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t care write burst identified (we# = low) t cbph t khtl t hz t cew t kp t khkl t cem table 33: burst wri te timing parameters symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t cbph 555ns t hz 888ns t cem 888s t khkl 1.6 1.6 1.6 ns t cew 17.517.517.5ns t khtl 7911ns t clk 9.62 20 12.5 20 15 20 ns t kp 3 4 5 ns t csp 4204.520520ns t sp 3 3 3 ns t hd 222ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 44 ?2004 micron technology, inc. all rights reserved. figure 37: continuous burst write showing an output delay with bcr[8] = 0 for end-of-row condition 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. 3. wait will be asserted (2 x lc) + 1 cycles (bcr[8] = 0; wa it asserted during delay). lc = latency code (bcr[13:11]). 4. ce# must not remain low longer than t cem. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t khtl t khtl t clk t sp t hd valid input d[n] note 3 note 4 valid input d[n+2] end of row valid input d[n+1] valid input d[n+3] don?t care v ih v il lb#/ub# table 34: burst write timi ng parameters?bcr[8] = 0 symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t clk 9.62 20 12.5 20 15 20 ns t khtl 7911ns t hd 222ns t sp 3 3 3 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 45 ?2004 micron technology, inc. all rights reserved. figure 38: burst write followed by burst read 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr[15] = 0), a refresh opportunity must be pr ovided every tcem. a refresh opportunity is satisfied by ei ther of the following two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. 3. clock rates below 50 mhz ( t clk > 20ns) are allowed as long as t csp specifications are met. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il t clk t sp t sp t hd t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t sp t hd valid address t aba t csp t ohz t koh t aclk valid output valid output valid output valid output high-z high-z v oh v ol lb#/ub# v ih v il t hd t sp t hd t sp t hd t hd high-z undefined don?t care t boe t cbph 2 high-z t sp t hd table 35: write timing parameters?bur st write followed by burst read symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t cbph 555ns t hd 222ns t clk 9.62 20 12.5 20 15 20 ns t sp 3 3 3 ns t csp 4204.520520ns table 36: read timing parameters?bur st write followed by burst read symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hd 222ns t aclk 7911ns t koh 2 2 2 ns t boe 20 20 20 ns t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t sp 333ns t csp 4204.520520ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 46 ?2004 micron technology, inc. all rights reserved. figure 39: asynchronous wr ite followed by burst read 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. when configured for synchronous mode ( bcr[15] = 0), a refresh opportunity must be provided every tc em. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. 3. clock rates below 50 mhz ( t clk > 20ns) are a llowed as long as t csp specifications are met. t clk t sp t hd t sp t hd valid address t ohz t koh t aclk high-z high-z valid address valid address t avs t avh t aw t wr t vp t vs t cka a[21:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t as t as t wp t wc t dh t dw data data high-z t cvs t hd t sp t cew t sp t hd t csp t wc t wc t bw t whz valid output valid output valid output valid output don?t care undefined t aba t boe t cbph 2 t vph table 37: write timing parameters?asy nc write followed by burst read symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t dw 20 23 ns t avh 55ns t vp 10 10 ns t avs 10 10 ns t vph 10 10 ns t aw 70 85 ns t vs 70 85 ns t bw 70 85 ns t wc 70 85 ns t cka 70 85 ns t whz 88 ns t cvs 10 10 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns t wr 0 0 ns table 38: read timing parameters?asy nc write followed by burst read symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t csp 4204.520520 ns t aclk 7911ns t hd 222 ns t boe 20 20 20 ns t koh 2 2 2 ns t cbph 555ns t ohz 888 ns t cew 17.517.517.5ns t sp 3 3 3 ns t clk 9.62 20 12.5 20 15 20 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 47 ?2004 micron technology, inc. all rights reserved. figure 40: asynchronous write followed by burst read?adv# low 1 note: 1. non-default bcr settings: latency code two (three cloc ks); wait active low; wa it asserted during delay. 2. when configured for synchronous mode ( bcr[15] = 0), a refresh opportunity must be provided every tc em. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. 3. clock rates below 50 mhz ( t clk > 20ns) are a llowed as long as t csp specifications are met. t clk t sp t hd valid address t csp t koh t aclk valid output high-z valid address valid address t cka a[21:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t wp t wc t dh t dw data data high-z t hd t sp t sp t hd t wc t wc t bw t whz t aw t wr t sp t hd valid output valid output valid output undefined don?t care t boe t ohz t cew t cbph 2 high-z t aba table 39: asynchronous write timing parameters?adv# low symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88 ns t cka 70 85 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 0 0 ns t dw 23 23 ns table 40: burst read timing parameters symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t csp 4204.520520 ns t aclk 7911ns t hd 2 2 2 ns t boe 20 20 20 ns t koh 2 2 2 ns t cbph 555ns t ohz 888 ns t cew 1 7.5 1 7.5 1 7.5 ns t sp 333 ns t clk 9.62 20 12.5 20 15 20 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 48 ?2004 micron technology, inc. all rights reserved. figure 41: burst read followed by asynchronous write (we#-controlled) note: 1. when configured for synchronous mode (bcr[15] = 0) , a refresh opportunity mu st be provided every t cem. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns . a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba t aw t cw t wr valid output valid address high-z t koh t dw t ohz t sp t hd lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) t wc t khtl t boe valid address valid input high-z t cew t hz t cbph 1 table 41: burst read timing parameters symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hd 222 ns t aclk 7911ns t hz 8 8 8 ns t boe 20 20 20 ns t khtl 7911ns t cbph 555ns t koh 2 2 2 ns t cew 17.517.517.5ns t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t sp 333 ns t csp 4204.520520ns table 42: asynchronous write timing parameters?we# controlled symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t hz 88ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 0 0 ns t dw 23 23 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 49 ?2004 micron technology, inc. all rights reserved. figure 42: burst read followed by asynchronous write using adv# note: 1. when configured for synchronous mode (bcr[15] = 0), a refresh opportunity mu st be provided every t cem. a refresh opportu- nity is satisfied by either of the fo llowing two conditions: a) clocked ce# high, or b) ce# high for greater than 15ns. a[21:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t cew t hd t aba t vph t vs t avs t avh t aw t cw valid output valid address high-z t koh t dw t ohz t sp t hd t vp lb#/ub# v ih v il t csp t olz t hd t wp t wph t as t dh t hd t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) t khtl valid address valid input high-z t cew t hz t cbph 1 t aclk t boe t as high-z table 43: burst read timing parameters symbol -701 -708 -706, -856 units symbol -701 -708 -706, -856 units min max min max min max min max min max min max t aba 35 46.5 56 ns t hd 222 ns t aclk 79 11ns t hz 8 8 8 ns t boe 20 20 20 ns t khtl 7911ns t cbph 555 ns t koh 2 2 2 ns t cew 17.517.517.5 ns t ohz 8 8 8 ns t clk 9.62 20 12.5 20 15 20 ns t sp 333 ns t csp 4204.520520 ns table 44: asynchronous write timing parameters using adv# symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t dw 23 23 ns t avh 5 5 ns t hz 88ns t avs 10 10 ns t vp 10 10 ns t aw 70 85 ns t vph 10 10 ns t bw 70 85 ns t vs 70 85 ns t cew 1 7.5 1 7.5 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 0 0 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 50 ?2004 micron technology, inc. all rights reserved. figure 43: asynchronous write followed by asyn chronous read?adv# low note: 1. when transitioning between asynchronous cy cles, ce# must remain high for at least 5ns ( t cph) to schedule the appropriate internal refresh oper ation. bcr[15] can be 1 or 0. valid address valid address a[21:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# v ih v il v ih v il v ih v il v ih v il t cw t wph t wp t wc t dh t dw data high-z valid address t aa t bhz t cph 1 t co valid output high-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw t whz t hz t hz don?t care undefined data table 45: write timing parameters?adv# low symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88 ns t cw 70 85 ns t wp 46 55 ns t dh 0 0 ns t wph 10 10 ns t dw 23 23 ns t wr 0 0 ns t hz 88ns table 46: read timing parameters?adv# low symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aa 70 85 ns t hz 88 ns t bhz 88 ns t lz 10 10 ns t blz 10 10 ns t oe 20 20 ns t co 70 85 ns t ohz 88ns t cph 55ns t olz 585 ns 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 51 ?2004 micron technology, inc. all rights reserved. figure 44: asynchronous write followed by asynchronous read note: 1. when transitioning between asynchronous cycles, ce# must remain high for at least 5ns ( t cph) to schedule the appro- priate internal re fresh operation. bcr[15] can be 1 or 0. valid address valid address t avs t avh t vph t vp t vs a[21:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# t vp t avh t cw t wph t as t wp t wc t dh t dw data data high-z valid address t aa t bhz t aadv t cph 1 t co valid output high-z t cvs t olz t lz t as t blz t ohz t hz t aw t wr t bw t whz undefined don?t care t oe t avs t cvs table 47: write timing parameters?asy nc write followed by async read symbol -70x -856 units symbol -70x -856 units min max min max min max min max t as 00ns t vp 10 10 ns t avh 55ns t vph 10 10 ns t avs 10 10 ns t vs 70 85 ns t aw 70 85 ns t wc 70 85 ns t bw 70 85 ns t whz 88ns t cvs 10 10 ns t wp 46 55 ns t cw 70 85 ns t wph 10 10 ns t dh 00ns t wr 00ns t dw 23 23 ns table 48: read timing parameters?asy nc write followed by async read symbol -70x -856 units symbol -70x -856 units min max min max min max min max t aa 70 85 ns t cvs 10 10 ns t aadv 70 85 ns t hz 88 ns t avh 55ns t lz 10 10 ns t avs 10 10 ns t oe 20 20 ns t bhz 88 ns t ohz 88 ns t blz 10 10 ns t olz 5 5 ns t cbph 55ns t vp 10 10 ns t co 70 85 ns ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www .micron.com, customer comment line: 800-932-4992 micron, and the micron and m logos are trademarks and/or service marks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of infineon technologies outside the u.s . all other trademarks are the property of their respective owners. 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 52 ?2004 micron technology, inc. all rights reserved. figure 45: 54-ball vfbga note: 1. all dimensions in millimeters; max/min, or typical, as noted. 2. package width and length do not in clude mold protrusion; allowable mold protrusion is 0.25mm per side. data sheet designation: preliminary this data sheet contains initial characterization limits that are subject to change upon full character- ization of production devices. 0.700 0.075 0.10 c c solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2% ag solder ball pad: ? 0.27mm ball a1 id encapsulation material: epoxy novola c substrate: plastic laminate 0.75 typ 8.00 0.10 ball a1 id 0.75 typ 0.35 typ 54x ? 1.00 max seating plane ball a6 solder ball diameter refers to post reflow condition. the pre-reflow diameter is ? 0.33 ball a1 6.00 3.00 0.05 1.875 0.050 3.00 0.05 6.00 0.10 4.00 4 meg x 16, 2 meg x 16 async/page/burst cellularram memory preliminary 09005aef80be1fbd micron technology, inc., reserves the right to change products or specifications without notice. burst cellularram.fm - rev. d 5/19/04 en 53 ?2004 micron technology, inc. all rights reserved. revision history rev. c, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/04 added software access. cr write diagram titles updated to reflect writes followed by read array operation. added 80 mhz burst clock (-708). changed par options to full, one-half, one-quarter, one-eight, or none. corrected table 4 typo. added note 3 to fig. 31 and 37. added t co to fig. 43 and table 46. clarified read/write operating currents. added clarifying notes for required refresh opportunity for bcr[15], depending on bcr setting. changed t cem max to 8. updated i cc values and symbols. added adv# timing parameters and t co to fig. 44 and table 48. clarified ce# low time limited by refresh?must not stay low longer than t cem. aligned t aclk, t khtl, t aba, and t csp with consortium values. added t cem to asynchronous write, page mode read operation, and burst mode operation descriptions and timing diagrams. deleted appendix a (extended timings and all references). added -708 timing specifications. added c in and c io min values. clarified burst latency at row-boundary crossings. replaced abbreviated component marks with part numbering chart. added measurement time clarification to i sb and i par notes changed t cbph to t cph for async?async transitions. corrected package nomenclature to vfbga. clarified address a[4] and higher in page mode. clarified cre in figure 14. updated tkp to 4ns for the -708, and 5ns for -706 and -856 parts. rev. b, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/03 changed bcr[6] = 0 to ?not supported,? and deleted all references to falling clock edges. clarified mixed-mode operation. 104mhz part now ?contact factory.? changed t hd min in all speed grades to 2. prohibited dpd via software access sequence. changed t csp (min) to 5ns for -706 and -856 in all burst timing tables (18, 20, 25, 26, 27, 28, 34, 36, 37, 39, 41.) added ?and adv# low? to t as in async write timing req. table; added t as as appropriate in figures 34, 38, 41, 43, and corollary tables 38, 44, 48. added note 6 to tables 2 and 3 for standby mode, and clarified standby description under low-power operation. -701 latency code 2 (3 clocks) changed to 66 mhz (15.2ns) rev. a, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9/03 added lead-free option. differentiated standard and low-power standby and related annotation in/for figures and tables. clk in tables 2 & 3 changed; can be either high or low. data and figures added to cover software access to the configuration registers. l, v and -60 now ?contact factory.? added v & l options. modified wait in bus operations. indicated wrap factors. added -706 part inform ation where applicable. removed t sp and t hd from ce# in burst diagrams. |
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